Phase error (phase offset) is the time difference between relevant edges of the reference input clock and the feedback input to the phase detector of a phase lock loop (PLL). There are two type of phase error: static phase error and dynamic phase error. Static phase error is the time difference between the averaged input reference clock and the averaged feedback input signal when the PLL is in locked mode. Static phase error excludes jitter components. Dynamic phase error is the phase difference between the input clock and output clock due to inability of the PLL to instantaneously update the output clock when the period of the input clock changes. Dynamic phase error is also referred to as tracking skew, and includes jitter.
Phase jitter is the deviation in static phase offset for a controlled edge with respect to a mean value of static phase offset. Static phase error is caused by non-ideal elements in the PLL, such as the charge pump, phase detector, dividers in path, etc. Dynamic phase error is caused by reference clock jitter, VCO jitter, supply noise variations, etc. While zero phase error is ideal, the realistic offset for any PLL system is a measure of the ability of the loop to align the phases of the reference clock to the feedback clock. The wider this offset, the wider the phase relationship of a PLL output clock to the reference clock. The magnitude of the variation of phase offset is thus defined as phase jitter.
A lock detect circuit may be used to determine the lock state of a PLL. Information regarding the lock state of a PLL is used in a variety of applications, such as a macro test pass/fail criteria for manufacturing screen of wafers and modules in test. The lock signal may also be used as an indicator to a higher level system that stable clocking has been achieved and hence subsequent operations may be performed. During power-up or event changes (such as reference clock frequency change/divider value change/output frequency change) the PLL must achieve a lock state before the PLL clock signals or derivatives are suitable for use in downstream processing. Downstream circuits may go on standby mode for a preprogrammed wait time while the PLL is achieving lock.
Lock detect circuits are typically implemented as pure digital circuits that use digital counters. The counters generate pulses on different count codes and ensure that those pulses do not overlap. However, no pulses are generated at times when no feedback clock is present, which may cause the lock indicator to falsely report a lock condition.